1. Field of the Invention
The present invention relates to semiconductor memory device and, more particularly to a dynamic semiconductor memory device in which row and column selections are time multiplexedly performed. More specifically, the present invention relates to a dynamic semiconductor memory device used for an image processing application.
2. Description of the Background Art
FIG. 22 is a diagram schematically showing an arrangement of an array portion of a conventional dynamic semiconductor memory device (hereinafter abbreviated as DRAM). A word line WL and bit lines BL and ZBL are shown in FIG. 22. A memory cell MC is arranged corresponding to an intersection of bit line BL and word line WL. Memory cell MC includes a memory cell capacitor MQ for storing information and an access transistor MT for connecting memory cell capacitor MQ to bit line BL in response to a signal on word line WL. A cell plate voltage Vcp is applied to a cell plate node of memory cell capacitor MQ. Electric charges corresponding to the stored information are accumulated in an electrode (a storage node) connected to access transistor MT of memory cell capacitor MQ.
Bit lines BL and ZBL are arranged in a pair for transmitting complementary data signals. Memory cell MC is arranged corresponding to an intersection between one of bit lines BL and ZBL and a word line.
A sense amplifier circuit SA is arranged for bit lines BL and ZBL. Sense amplifier circuit SA differentially amplifies and latches a small voltage read onto bit lines BL and ZBL when activated. Bit lines BL and ZBL are connected to an internal data line pair IOP through a column selection gate CSG that is rendered conductive in response to a column selection signal Y on a column selection line CSL. Internal data line pair IOP is connected to a writing/reading circuit WRK including a write driver and a preamplifier.
FIG. 23 is a diagram showing signal waveforms related to a data access operation of DRAM shown in FIG. 22. The data access operation of the DRAM shown in FIG. 22 will now be described with reference to the signal waveform diagram shown in FIG. 23. Here, in the data access operation, data is written to or read from a memory cell.
Word line WL is selected in accordance with a row access instruction signal, and the voltage level thereof increases. When the voltage of word line WL rises, access transistor MT of memory cell MC is rendered conductive, so that accumulated electric charges of corresponding memory cell capacitor MQ are transmitted to corresponding bit line BL (or ZBL). The voltage level of bit line BL or ZBL changes in accordance with the stored data of the memory cell. FIG. 23 shows signal waveforms when data at an H level is read onto bit line BL.
The memory cell data is read to one of bit lines BL and ZBL, but no memory cell data is read onto the other bit line. The other bit line maintains a precharge voltage level (at an intermediate voltage level).
When the voltage (read voltage) read onto bit line BL (or ZBL) becomes sufficiently large, sense amplifier circuit SA is activated for differentially amplifying the voltages of bit line BL and ZBL. In differential amplification of sense amplifier circuit SA, the voltage of the bit line to which the memory cell data is read is amplified with reference to a potential of the bit line maintained at the precharge voltage. After the sensing operation, sense amplifier circuit SA maintains the voltages of bit lines BL and ZBL at the levels of a power supply voltage and a ground voltage in accordance with the memory cell data. A period till completion of the sensing operation of sense amplifier circuit SA and definition of the potentials of bit lines BL and ZBL is referred to as a column interlock period, during which column selection operation is prohibited.
When the column interlock period is elapsed, external column selection (column access) can be performed. In column access (column selection operation), column selection signal Y is activated in accordance with an applied column address signal, column selection gate CSG is rendered conductive in accordance with column selection signal Y on column selection line CSL, and bit lines BL and ZBL are connected to internal data line pair IOP. In this state, writing/reading circuit WRK is activated. In data writing, a write driver included in writing/reading circuit WRK is activated for setting the potentials of signals latched by sense amplifier circuit SA to voltage levels in according to the write data. In data reading, the signals latched by sense amplifier circuit SA are transmitted through internal data line pair IOP and amplified by the preamplifier included in writing/reading circuit WRK. FIG. 23 depicts signal waveforms in data writing by dotted lines.
In the DRAM, electric charges accumulated in memory cell capacitor MQ are read to corresponding bit line BL (or ZBL), and amplified and latched by sense amplifier circuit SA. Since sense amplifier circuit SA differentially amplifies a small voltage difference between bit lines BL and ZBL, during the sensing operation, column access is prohibited to prevent data destruction. Thus, in the DRAM, row access of selecting a word line and then performing the sensing operation by sense amplifier circuit SA and column access of selecting a column (a bit line pair) in accordance with the column address signal are time division multiplexedly performed. In addition, the amplified voltages of bit lines BL and ZBL are re-written to memory cell MC by the latching operation of sense amplifier circuit SA, so that the destructively read memory cell data is restored.
The DRAM is widely used as a mass storage memory since memory cell MC includes one access transistor MT and one memory cell capacitor MQ so that the silicon real estate of the memory cell is small and a cost per bit is low.
FIG. 24 is a diagram showing an exemplary operation sequence of the DRAM. Referring to FIG. 24, a row access instruction signal RACT and a data reading instruction signal READ are applied. In the case of a standard DRAM, row access instruction signal RACT is applied by the activation of a row address strobe signal /RAS. In the case of a synchronous DRAM (SDRAM or the like) operating in synchronization with a clock signal, the row access instruction signal is applied by active command ACT. In the case of the standard DRAM, reading operation designation signal READ is applied by a column address strobe signal /CAS and a write enable signal /WE (and output enable signal /OE). In the case of the SDRAM, reading operation designation signal READ is applied by a read command.
When row access instruction signal RACT is applied, word line WL is selected. Thereafter, reading operation designation signal READ is applied, and column selection signal Y is driven into a selected state in accordance with a concurrently applied column address. When a prescribed period of time is elapsed after column selection is performed in accordance with reading operation designation signal READ, data Q is externally read. The time required after reading operation designation signal READ is applied and before valid data is externally output is referred to as a CAS access time tCAC in the standard DRAM. On the other hand, the time required after row access instruction signal RACT is applied and before valid data is externally output is referred to as an RAS access time tRAC in the standard DRAM.
Accordingly, to externally output valid data after activation of row access instruction signal RACT, column selection must be performed after row selection and sense amplifier activation are performed. RAS access time tRAC is relatively long. On the other hand, during CAC access time tCAC, a memory cell is merely selected from a row in the selected state for data reading. Specifically, access time tCAC is the time required for data to be output from an output buffer through the reading circuit included in writing/reading circuit WRK from sense amplifier circuit SA, and is relatively short. Accordingly, when memory cell data is read with reading operation designation signal READ being successively applied to the same word line, data can be read at a relatively high speed. Such an operation mode is referred to as a page mode or a static column mode in the standard DRAM. In the SDRAM, when the burst operation is performed, data by burst length are successively read in accordance with an internally generated column address. The page mode operation can be performed also in the SDRAM.
However, when another row is selected, the word line in the selected state is temporarily driven into the non-selected state by applying precharge designation signal PRC, and row access instruction signal RACT must be again applied. Precharge designation signal PRC is applied upon inactivation of row address strobe signal /RAS in the standard DRAM, and applied by a precharge command in the SDRAM or the like.
A time referred to as RAS precharge time tRP is required after the precharge designation signal is applied and before the row access instruction signal is applied next. During the RAS precharge period, a row related circuit is once brought back into a stand-by state. Thus, although fast data access is performed when successively accessing the same row (word line), inactivation of the word line and selection of another word line must be performed in changing rows (page switching), during which data cannot be accessed. Thus, fast data transfer is not achieved.
To cope with the problem related to the decrease in data transfer speed caused by such an operation of the row related circuit, a multibank DRAM or the like has been proposed, in which a cache DRAM with a cache contained in the DRAM and a memory array within a chip are divided into a plurality of banks and a time division multiplexed operation (an interleave operation) is performed every bank.
However, the cache DRAM internally requires an SRAM (a static RAM) arranged as a cache and a control circuit for determination of cache miss/hit as well as for data transfer between the DRAM and the cache based on the determination result. Thus, a chip area increases.
In the case of the multibank DRAM, an overhead in page switching is not caused for successive access to different banks as in the case of time division multiplexed accessing to the banks (this is because a word line is selected in another bank in accessing one bank). However, when accessing a different row in the same bank, the problem associated with the overhead in page switching is caused. To enhance the effect of the multibank configuration and to increase the number of banks so as to minimize the occurrence of successive accesses to the same bank, a sense amplifier circuit group must be provided for each bank. Thus, the area of the memory array increases and the area of the bank control circuit also increases disadvantageously.